HyperAccel LPU IP & Forte LLM Inference Accelerators

HyperAccel Inc. is an AI semiconductor company headquartered in Seocho-gu, Seoul, led by CEO Kim Joo-young. It designs LLM Processing Unit (LPU) technology to cut the cost, power and latency of large language model inference compared with general-purpose GPUs.

The LPU is a coarse-grained, programmable processor that runs every LLM inference operation within each core, maximises data reuse and overlaps communication with computation to scale across chips. It is offered as licensable processor IP with PCIe and UCIe integration and latency-optimised, balanced and high-performance variants; as the Forte 55X accelerator built on an AMD Alveo U55C card with 16 GB HBM2; and as the HX-F55X server with ASUS. The Bertha 500 ASIC is in development. A software stack provides PyTorch, vLLM and Hugging Face support, an embedded DSL for LPU kernels, runtime and driver, and supports transformer models such as Llama, Qwen, Mistral, DeepSeek and Gemma.

• LPU IP: modular LLM processor IP with latency-optimised, balanced and high-performance variants.
• SoC integration: standard PCIe and UCIe protocols and support for all DRAM types.
• Forte 55X: FPGA-based accelerator with 16 GB HBM2 at 460 GB/s and 75 W power.
• HX-F55X server: datacenter inference system combining Forte 55X cards with an ASUS server.
• Bertha ASIC: dedicated LLM inference chip family under development.
• Software stack: PyTorch, vLLM and Hugging Face support with an embedded DSL, runtime and driver.

A Vietnamese cloud provider can deploy HX-F55X servers to offer lower-cost LLM inference services. A bank or telecom operator can run on-premise chatbots on Forte accelerators to keep data local. A Vietnamese chip design company can license LPU IP for an edge AI SoC in robots or smart appliances.

In vendor benchmarks with eight cards, Forte 55X delivers about 1.7x the throughput of NVIDIA L4 on OPT models and about 1.4x more tokens per second per kilowatt. LPU IP variants range from 2.84 W to 4.72 W with 6 to 12 TFLOPS FP16 per core, suiting edge devices through cloud servers. Standard PCIe and UCIe interfaces simplify SoC integration. Support for vLLM and Hugging Face eases model deployment.

LLM inference is becoming the largest share of AI compute cost, driving demand for specialised accelerators that are cheaper and more power-efficient than GPUs. Governments and enterprises want domestic or on-premise AI infrastructure. Vietnam's data centre and sovereign AI ambitions, together with its electronics manufacturing base, create openings for inference accelerators and licensable LPU IP.

Headquartered at 299 Gangnam-daero, Seocho-gu, Seoul; CEO Kim Joo-young. Partners named on its site include AMD and ASUS, with reported work involving Samsung's 4 nm process, LG, Naver Cloud and Hyundai Motor. Named to Forbes Korea's 2026 Korea AI 50, selected for the 2026 Unicorn Bridge programme, and the CEO received a 2026 Information and Communications Day service medal.