Rise AI IPCreate & High-Level Design Platform

Rise Design Automation, Inc. is an EDA company based in Pleasanton, California, led by co-founder and CEO Badru Agarwala, who previously ran the Calypto Systems Division at Mentor Graphics. It aims to raise chip design above RTL so that hardware teams can move from specification to verified implementation much faster.

The Rise AI IPCreate platform turns structured specifications, algorithms or existing high-level code into an HLS model in C++, SystemC or SystemVerilog. The deterministic Rise High-Level Platform then synthesises technology-aware, PPA-optimised RTL together with a matching verification environment. An orchestration layer runs module and testbench generation, simulation and design-space exploration in a Propose, Evaluate, Decide loop driven by measured PPA, while an Optimization Agent analyses the Pareto front. The platform is model-agnostic and integrates hls4ml and OpenROAD for ML model import and place-and-route estimation.

• Spec-to-HLS generation: turns specifications, algorithms or existing code into C++, SystemC or SystemVerilog HLS models.
• High-level synthesis: produces PPA-optimised RTL plus a matching verification environment.
• Closed-loop orchestration: Propose, Evaluate, Decide loop re-runs only failed steps using tool diagnostics.
• Optimization Agent: design-space exploration and Pareto front analysis against user goals.
• Domain knowledge base: IP and expertise for compute, AI acceleration, image and signal processing.
• Open integrations: model-agnostic AI harness, hls4ml for ML models and OpenROAD for physical estimation.

A Vietnamese chip startup can turn an image processing algorithm into an AXI accelerator block without hand-writing RTL. A university chip design programme can teach hardware design from C++ models with fast verification. A design services company can explore multiple PPA options for a customer's signal processing IP in days.

The company states that high-level verification runs 30x to 1,000x faster than RTL simulation and that projects shrink from years to months. RTL synthesis estimates correlate within 10% of production synthesis tools, so architecture decisions can be made early. High-level synthesis finishes in seconds, allowing tens to hundreds of design candidates to be compared. Outputs remain transparent and editable, with reproducible scripts.

Custom accelerators for AI, vision and signal processing are multiplying, but RTL-level design and verification remain slow. High-level synthesis combined with generative AI is emerging as a way to raise productivity for small hardware teams. Vietnam's new chip design workforce, often stronger in software than in RTL, can benefit from flows that start from C++ or SystemC.

Based in Pleasanton, California. Co-founder and CEO Badru Agarwala has 40 years in EDA, including leading the Calypto Systems Division at Mentor Graphics and co-founding Axiom Design Automation. The company debuted at DAC 2025 and is part of the Microsoft for Startups Founders Hub.